1. Field of the Invention
The present invention relates to data processing technology, and more particularly, to a data processing apparatus and method using a first-in first-out (FIFO) device.
2. Description of the Related Art
Memory controllers that control the operations of memory devices processing data at a double data rate (DDR), such as DDR memory devices, DDR2 memory devices, DDR3 memory devices, graphics DDR (GDDR) memory devices, GDDR2 memory devices, and GDDR3 memory devices, perform a read operation by latching input data in synchronization with a clock signal generated by shifting by 90 degrees the phase of a data strobe signal output from the memory devices. In order to increase the device timing margin, it is important to control skew between data strobe signals input to clock terminals of a plurality of flip-flops, respectively, which are responsible for latching the input data, and to control skew between data signals input to input terminals of the respective flip-flops. The clock terminals and the input terminals are portions of the device at which signal skew is controlled.
With the increase of operating speed of memory devices and memory controllers, FIFO devices are commonly employed so that input and output data can be latched at a high rate. However, since a FIFO device includes a plurality of flip-flops, the number of points requiring skew control increases. As a result, it is difficult to control skew between data strobe signals input to clock terminals of the respective flip-flops and to control skew between data input to input terminals of the respective flip-flops. Moreover, when the depth of the FIFO device increases, the number of points requiring skew control also increases.